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Section 18 Serial Sound Interface
R01UH0134EJ0400 Rev. 4.00 Page 917 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
18.3.7 Transmit FIFO Data Register (SSIFTDR)
SSIFTDR is a FIFO register consisting of eight stages of 32-bit registers for storing data to be
serially transmitted. On detecting that the transmit data register (SSITDR) is empty, this module
transfers the data for transmission written to SSIFTDR to SSITDR to start serial transmission,
which can continue until SSIFTDR becomes empty. SSIFTDR can be written to by the CPU at
any time.
Note that when SSIFTDR is full of data (32 bytes), the next data cannot be written to it. If writing
is attempted, it will be ignored and an overflow occurs.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bit:
Initial value:
R/W:
1514131211109876543210
Bit:
Initial value:
R/W:
Note: Not writable during reception.*
----------------
WWWWWWWWWWWWWWWW
----------------
WWWWWWWWWWWWWWWW
18.3.8 Receive FIFO Data Register (SSIFRDR)
SSIFRDR is a FIFO register consisting of eight stages of 32-bit registers for storing serially
received data. When four bytes of data have been received, this module transfers the received data
in the receive data register (SSIRDR) to SSIFRDR to complete reception operation. Reception can
continue until 32 bytes of data have been stored to SSIFRDR. SSIFRDR can be read by the CPU
but cannot be written to. Note that when SSIFRDR is read when it stores no received data,
undefined values will be read and a receive underflow occurs.
After SSIFRDR becomes full of received data, the data received thereafter will be lost and a
receive overflow occurs.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bit:
Initial value:
R/W:
1514131211109876543210
Bit:
Initial value:
R/W:
----------------
RRRRRRRRRRRRRRRR
----------------
RRRRRRRRRRRRRRRR