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Section 26 USB 2.0 Host/Function Module
R01UH0134EJ0400 Rev. 4.00 Page 1387 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
1 PIPE1NRDYE 0 R/W NRDY Interrupt Enable for PIPE1
0: Interrupt output disabled
1: Interrupt output enabled
0 PIPE0NRDYE 0 R/W NRDY Interrupt Enable for PIPE0
0: Interrupt output disabled
1: Interrupt output enabled
26.3.14 BEMP Interrupt Enable Register (BEMPENB)
BEMPENB is a register that enables or disables the BEMP bit in INTSTS0 to be set to 1 when the
BEMP interrupt is detected for each pipe.
On detecting the BEMP interrupt for the pipe corresponding to the bit in this register that has been
set to 1, this module sets 1 to the corresponding PIPEBEMP bit in BEMPSTS and the BEMP bit in
INTSTS0, and generates the BEMP interrupt.
While at least one PIPEBEMP bit in BEMPSTS indicates 1, this module generates the BEMP
interrupt when the corresponding interrupt enable bit in BEMPENB is modified from 0 to 1.
This register is initialized by a power-on reset.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit:
Initial value:
R/W:
0000000000000000
R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
——————
PIPE9
BEMPE
PIPE8
BEMPE
PIPE7
BEMPE
PIPE6
BEMPE
PIPE5
BEMPE
PIPE4
BEMPE
PIPE3
BEMPE
PIPE2
BEMPE
PIPE1
BEMPE
PIPE0
BEMPE
Bit Bit Name
Initial
Value
R/W Description
15 to 10 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
9 PIPE9BEMPE 0 R/W BEMP Interrupt Enable for PIPE9
0: Interrupt output disabled
1: Interrupt output enabled