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Section 15 Serial Communication Interface with FIFO
R01UH0134EJ0400 Rev. 4.00 Page 761 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
15.4.3 Operation in Clock Synchronous Mode
In clock synchronous mode, data is transmitted and received in synchronization with clock pulses.
This mode is suitable for high-speed serial communication.
The transmitter and receiver in this module are independent, so full-duplex communication is
possible while sharing the same clock. The transmitter and receiver are also 16-byte FIFO
buffered, so continuous transmitting or receiving is possible by reading or writing data while
transmitting or receiving is in progress.
Figure 15.11 shows the general format in clock synchronous serial communication.
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
*
*
LSB
MSB
Don't careDon't care
One unit of transfer data (character or frame)
Serial data
Serial clock
Note: * High except in continuous transfer
Figure 15.11 Data Format in Clock Synchronous Communication
In clock synchronous serial communication, each data bit is output on the communication line
from one falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of
the serial clock.
In each character, the serial data bits are transmitted in order from the LSB (first) to the MSB
(last). After output of the MSB, the communication line remains in the state of the MSB.
In clock synchronous mode, data is received in synchronization with the rising edge of the serial
clock.