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Section 33 Power-Down Modes
R01UH0134EJ0400 Rev. 4.00 Page 1773 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
33.2.1 Standby Control Register 1 (STBCR1)
STBCR1 is an 8-bit readable/writable register that specifies the state of the power-down mode.
Note: When writing to this register, see section 33.4, Usage Notes.
76543210
Bit:
Initial value:
R/W:
00000000
R/W R/W R R R R R R
STBY DEEP - -----
Bit Bit Name
Initial
Value R/W Description
7
6
STBY
DEEP
0
0
R/W
R/W
Software Standby, Deep Standby
Specifies transition to software standby mode or
deep standby mode.
0x: Executing SLEEP instruction puts chip into
sleep mode.
10: Executing SLEEP instruction puts chip into
software standby mode.
11: Executing SLEEP instruction puts chip into deep
standby mode.
5 to 0 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
[Legend]
x: Don't care