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Section 33 Power-Down Modes
Page 1798 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
33.2.16 Deep Standby Control Register (DSCTR)
DSCTR is an 8-bit readable/writable register that selects whether the states of the external
memory control pins are retained or not when returning from deep standby mode and specifies the
method to start the LSI.
Note: When writing to this register, see section 33.4, Usage Notes.
76543210
Bit:
Initial value:
R/W:
00000000
R/W R/W R R R R R R
-- --
EBUS
KEEPE
RAM
BOOT
--
Bit Bit Name
Initial
Value R/W Description
7 EBUSKEEPE 0 R/W Retention of External Memory Control Pin State
0: The state of the external memory control pins is not
retained when returning from deep standby mode.
1: The state of the external memory control pins is
retained when returning from deep standby mode.
6 RAMBOOT 0 R/W Selection of Method after Returning from Deep
Standby Mode
Selects an activation method after returning from
deep standby mode.
0: Activated according to the boot mode specified for
a reset.
1: The program is read from the on-chip data-
retention RAM.
[1-Mbyte version]
Program counter (PC): H'1C0F8000
Stack pointer (SP): H'1C0F8004
[640-Kbyte version]
Program counter (PC): H'1C000000
Stack pointer (SP): H'1C000004
5 to 0 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.