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Section 20 Controller Area Network
Page 1030 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
(2) Transmit Cancel Register (TXCR1, TXCR0)
The TXCR1 and TXCR0 are 16-bit read/conditionally-write registers. The TXCR1 controls
Mailbox-31 to Mailbox-16, and the TXCR0 controls Mailbox-15 to Mailbox-1.This register is
used by the CPU to request the pending transmission requests in the TXPR to be cancelled. To
clear the corresponding bit in the TXPR the CPU must write a '1' to the bit position in the TXCR.
Writing a '0' has no effect.
When an abort has succeeded the CAN controller clears the corresponding TXPR + TXCR bits,
and sets the corresponding ABACK bit. However, once a Mailbox has started a transmission, it
cannot be cancelled by this bit. In such a case, if the transmission finishes in success, the CAN
controller clears the corresponding TXPR + TXCR bit, and sets the corresponding TXACK bit,
however, if the transmission fails due to a bus arbitration loss or an error on the bus, the CAN
controller clears the corresponding TXPR + TXCR bit, and sets the corresponding ABACK bit. If
an attempt is made by the CPU to clear a mailbox transmission that is not transmit-pending it has
no effect. In this case the CPU will be not able at all to set the TXCR flag.
TXCR1
1514131211109876543210Bit:
Initial value:
R/W:
0000000000000000
R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
TXCR1[15:0]
Note: * Only writing a ‘1’ to a Mailbox that is requested for transmission and is configured as
transmit.
Bit 15 to 0 — Requests the corresponding Mailbox, that is in the queue for transmission, to cancel
its transmission. The bit 15 to 0 corresponds to Mailbox-31 to 16 (and TXPR1[15:0]) respectively.
Bit[15:0]:TXCR1 Description
0 Transmit message cancellation idle state in corresponding mailbox (Initial
value)
[Clearing Condition]
Completion of transmit message cancellation (automatically cleared)
1 Transmission cancellation request made for corresponding mailbox