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Page xxxviii of xl R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
35.3 Register Descriptions ...................................................................................................... 1832
35.3.1 PWM Control Register_n (PWCR_n) (n = 1, 2) ............................................. 1833
35.3.2 PWM Polarity Register_n (PWPR_n) (n = 1, 2) ............................................. 1834
35.3.3 PWM Counter_n (PWCNT_n) (n = 1, 2) ........................................................ 1835
35.3.4 PWM Cycle Register_n (PWCYR_n) (n = 1, 2) ............................................. 1835
35.3.5 PWM Duty Registers_nA, nC, nE, nG
(PWDTR_nA, PWDTR_nC, PWDTR_nE, PWDTR_nG) (n = 1, 2) .............. 1836
35.3.6 PWM Buffer Registers_nA, nC, nE, nG
(PWBFR_nA, PWBFR_nC, PWBFR_nE, PWBFR_nG) (n = 1, 2) ............... 1839
35.3.7 PWM Buffer Transfer Control Register (PWBTCR) ...................................... 1840
35.4 Bus Master Interface ....................................................................................................... 1841
35.4.1 16-Bit Data Registers ...................................................................................... 1841
35.4.2 8-Bit Data Registers ........................................................................................ 1841
35.5 Operation ........................................................................................................................ 1842
35.5.1 PWM Operation .............................................................................................. 1842
35.5.2 Buffer Transfer Control .................................................................................. 1843
35.6 Usage Note ..................................................................................................................... 1844
35.6.1 Conflict between Buffer Register Write and Compare Match ........................ 1844
Section 36 List of Registers ............................................................................. 1845
36.1 Register Addresses (by functional module, in order of
the corresponding section numbers) ............................................................................... 1846
36.2 Register Bits ................................................................................................................... 1880
36.3 Register States in Each Operating Mode ........................................................................ 1957
Section 37 Electrical Characteristics ............................................................... 1961
37.1 Absolute Maximum Ratings ........................................................................................... 1961
37.2 Power-On/Power-Off Sequence ...................................................................................... 1962
37.3 DC Characteristics .......................................................................................................... 1963
37.4 AC Characteristics .......................................................................................................... 1974
37.4.1 Clock Timing .................................................................................................. 1974
37.4.2 Control Signal Timing .................................................................................... 1979
37.4.3 Bus Timing ..................................................................................................... 1981
37.4.4 Direct Memory Access Controller Timing ..................................................... 2015
37.4.5 Multi-Function Timer Pulse Unit 2 Timing .................................................... 2016
37.4.6 Watchdog Timer Timing ................................................................................ 2017
37.4.7 Serial Communication Interface with FIFO Timing ....................................... 2018
37.4.8 Renesas Serial Peripheral Interface Timing .................................................... 2019
37.4.9 I
2
C Bus Interface 3 Timing ............................................................................. 2023
37.4.10 Serial Sound Interface Timing ........................................................................ 2025