Filter
Top Products
Section 6 Exception Handling
Page 144 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
6.4.2 Register Bank Error Exception Handling
When a register bank error occurs, register bank error exception handling starts. The CPU operates
as follows:
1. The exception service routine start address which corresponds to the register bank error that
occurred is fetched from the exception handling vector table.
2. The status register (SR) is saved to the stack.
3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
instruction to be executed after the last executed instruction for a bank overflow, and the start
address of the executed RESBANK instruction for a bank underflow.
To prevent multiple interrupts from occurring at a bank overflow, the priority level of the
interrupt that caused the bank overflow is written to the interrupt mask level bits (I3 to I0) of
the status register (SR).
4. After jumping to the exception service routine start address fetched from the exception
handling vector table, program execution starts. The jump that occurs is not a delayed branch.
6.5 Interrupts
6.5.1 Interrupt Sources
The sources that start interrupt exception handling are divided into NMI, user debugging interface,
IRQ, PINT, and on-chip peripheral modules.
Each interrupt source is allocated a different vector number and vector table offset. See table 7.4
in section 7, Interrupt Controller, for more information on vector numbers and vector table address
offsets.