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Section 26 USB 2.0 Host/Function Module
R01UH0134EJ0400 Rev. 4.00 Page 1367 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
31 to 0 FIFOPORT
[31:0]
All 0 R/W FIFO Port
Accessing these bits allow reading the received data
from the FIFO buffer or writing the transmit data to
the FIFO buffer.
These bits can be accessed only while the FRDY bit
in each control register (CFIFOCTR, D0FIFOCTR, or
D1FIFOCTR) is 1.
The valid bits in this register depend on the settings
of the MBW bits (access bit width setting) and
BIGEND bit (endian setting) as shown in tables 26.7
to 26.9.
Table 26.7 Endian Operation in 32-Bit Access (when MBW = 10)
BIGEND Bit Bits 31 to 24 Bits 23 to 16 Bits 15 to 8 Bits 7 to 0
0 N + 3 address N + 2 address N + 1 address N + 0 address
1 N + 0 address N + 1 address N + 2 address N + 3 address
Table 26.8 Endian Operation in 16-Bit Access (when MBW = 01)
BIGEND Bit Bits 31 to 24 Bits 23 to 16 Bits 15 to 8 Bits 7 to 0
0 Writing: invalid, reading: prohibited* N + 1 address N + 0 address
1 N + 0 address N + 1 address Writing: invalid, reading: prohibited*
Note: * Reading data from the invalid bits in a word or byte unit is prohibited.
Table 26.9 Endian Operation in 8-Bit Access (when MBW = 00)
BIGEND Bit Bits 31 to 24 Bits 23 to 16 Bits 15 to 8 Bits 7 to 0
0 Writing: invalid, reading: prohibited* N + 0 address
1 N + 0 address Writing: invalid, reading: prohibited*
Note: * Reading data from the invalid bits in a word or byte unit is prohibited.