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Section 9 Bus State Controller
R01UH0134EJ0400 Rev. 4.00 Page 275 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
14 to 11 TED[3:0] 0000 R/W Number of Delay Cycles from Address Output to
RD/WE Assertion
Specify the number of delay cycles from address
output to RD/WE assertion for the memory card or to
ICIORD/ICIOWR assertion for the I/O card in
PCMCIA interface.
0000: 0.5 cycle
0001: 1.5 cycles
0010: 2.5 cycles
0011: 3.5 cycles
0100: 4.5 cycles
0101: 5.5 cycles
0110: 6.5 cycles
0111: 7.5 cycles
1000: 8.5 cycles
1001: 9.5 cycles
1010: 10.5 cycles
1011: 11.5 cycles
1100: 12.5 cycles
1101: 13.5 cycles
1110: 14.5 cycles
1111: 15.5 cycles