Filter
Top Products
Section 9 Bus State Controller
R01UH0134EJ0400 Rev. 4.00 Page 315 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Figures 9.15 and 9.16 show a timing chart in burst read. In burst read, an ACTV command is
output in the Tr cycle, the READ command is issued in the Tc1, Tc2, and Tc3 cycles, the READA
command is issued in the Tc4 cycle, and the read data is received at the rising edge of the external
clock (CKIO) in the Td1 to Td4 cycles. The Tap cycle is used to wait for the completion of an
auto-precharge induced by the READA command in the SDRAM. In the Tap cycle, a new
command will not be issued to the same bank. However, access to another CS space or another
bank in the same SDRAM space is enabled. The number of Tap cycles is specified by the WTRP1
and WTRP0 bits in CS3WCR.
In this LSI, wait cycles can be inserted by specifying each bit in CS3WCR to connect the SDRAM
in variable frequencies. Figure 9.16 shows an example in which wait cycles are inserted. The
number of cycles from the Tr cycle where the ACTV command is output to the Tc1 cycle where
the READ command is output can be specified using the WTRCD1 and WTRCD0 bits in
CS3WCR. If the WTRCD1 and WTRCD0 bits specify one cycles or more, a Trw cycle where the
NOP command is issued is inserted between the Tr cycle and Tc1 cycle. The number of cycles
from the Tc1 cycle where the READ command is output to the Td1 cycle where the read data is
latched can be specified for the CS2 and CS3 spaces independently, using the A2CL1 and A2CL0
bits in CS2WCR or the A3CL1 and A3CL0 bits in CS3WCR. The number of cycles from Tc1 to
Td1 corresponds to the SDRAM CAS latency. The CAS latency for the SDRAM is normally
defined as up to three cycles. However, the CAS latency in this LSI can be specified as 1 to 4
cycles. This CAS latency can be achieved by connecting a latch circuit between this LSI and the
SDRAM.
A Tde cycle is an idle cycle required to transfer the read data into this LSI and occurs once for
every burst read or every single read.