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R01UH0134EJ0400 Rev. 4.00 Page 2085 of 2108
Sep 24, 2014
Item Page Revision (See Manual for Details)
33.2 Register Descriptions
Table 33.2 Register
Configuration
1772 Table amended
Register Name Abbreviation R/W
Initial
Value
Address
Access
Size
Standby control register 1 STBCR1 R/W H'00 H'FFFE0014 8
33.3.2 Software Standby
Mode
(1) Transition to Software
Standby Mode
1807 Description amended
3. After setting the STBY and DEEP bits in STBCR1 to 1
and 0 respectively, read STBCR1. Then, execute a
SLEEP instruction.
33.3.4 Deep Standby Mode
(2) Canceling Deep Standby
Mode
Figure 33.3 Flowchart of
Canceling Deep Standby
Mode
1813 Figure amended
Check the flags in DSFR
standby mode cancel source
Reconfiguration of
peripheral functions*
Clear the IOKEEP bit in DSFR
(Release the pin state retention)
To the state before the transition
to deep standby mode
Processing according to deep
(4) Notes on Transition to
Deep Standby Mode
1816 Description amended
If multiple canceling
sources have been specified and multiple canceling
sources are input, multiple cancel source flags will be set.
Section 36 List of Registers 1845 Description amended
4. Notes when Writing to the On-Chip Peripheral Modules
To access an on-chip module register, two or more
peripheral module clock (P) cycles are required. When
the CPU writes data to the internal peripheral registers,
the CPU performs the succeeding instructions without
waiting for the completion of writing to registers. For
example, a case is described here in which the system
is transferring to the software standby mode for power
savings. To make this transition, the SLEEP instruction
must be performed after setting the STBY bit in the
STBCR1 register to 1. However a dummy read of the
STBCR1 register is required before executing the
SLEEP instruction. If a dummy read is omitted, the
CPU executes the SLEEP instruction before the STBY
bit is set to 1, thus the system enters sleep mode not
software standby mode. A dummy read of the STBCR1
register is indispensable to complete writing to the
STBY bit.