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Section 6 Exception Handling
Page 132 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Type Exception Handling Priority
Instruction Trap instruction (TRAPA instruction) High
General illegal instructions (undefined code)
Slot illegal instructions (undefined code placed directly after a delayed
branch instruction*
1
(including FPU instructions and FPU-related CPU
instructions in FPU module standby state), instructions that rewrite the
PC*
2
, 32-bit instructions*
3
, RESBANK instruction, DIVS instruction, and
DIVU instruction)
Low
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF.
2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BF/S, BT/S, BSRF, BRAF, JSR/N, RTV/N.
3. 32-bit instructions: BAND.B, BANDNOT.B, BCLR.B, BLD.B, BLDNOT.B, BOR.B,
BORNOT.B, BSET.B, BST.B, BXOR.B, MOV.B@disp12, MOV.W@disp12,
MOV.L@disp12, MOVI20, MOVI20S, MOVU.B, MOVU.W.
6.1.2 Exception Handling Operations
The exception handling sources are detected and start processing according to the timing shown in
table 6.2.
Table 6.2 Timing of Exception Source Detection and Start of Exception Handling
Exception Source Timing of Source Detection and Start of Handling
Reset Power-on reset Starts when the RES pin changes from low to high, when the
user debugging interface reset negate command is set after the
user debugging interface reset assert command has been set,
or when the watchdog timer overflows.
Manual reset Starts when the watchdog timer overflows.
Address error Detected when instruction is decoded and starts when the
previous executing instruction finishes executing.
Interrupts
Register bank
error
Bank underflow Starts upon attempted execution of a RESBANK instruction
when saving has not been performed to register banks.
Bank overflow In the state where saving has been performed to all register
bank areas, starts when acceptance of register bank overflow
exception has been set by the interrupt controller (the BOVE bit
in IBNR of the interrupt controller is 1) and an interrupt that
uses a register bank has occurred and been accepted by the
CPU.