Filter
Top Products
Page xvi of xl R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
9.5.1 Endian/Access Size and Data Alignment .......................................................... 291
9.5.2 Normal Space Interface .................................................................................... 294
9.5.3 Access Wait Control ......................................................................................... 298
9.5.4 CSn Assert Period Expansion ........................................................................... 300
9.5.5 MPX-I/O Interface ............................................................................................ 301
9.5.6 SDRAM Interface ............................................................................................. 306
9.5.7 Burst ROM (Clocked Asynchronous) Interface ................................................ 342
9.5.8 SRAM Interface with Byte Selection ............................................................... 344
9.5.9 PCMCIA Interface ............................................................................................ 348
9.5.10 Burst ROM (Clocked Synchronous) Interface .................................................. 355
9.5.11 Wait between Access Cycles ............................................................................ 356
9.5.12 Bus Arbitration ................................................................................................. 364
9.5.13 Others ................................................................................................................ 366
Section 10 Direct Memory Access Controller ................................................... 371
10.1 Features ............................................................................................................................. 371
10.2 Input/Output Pins .............................................................................................................. 374
10.3 Register Descriptions ........................................................................................................ 375
10.3.1 DMA Source Address Registers (SAR) ............................................................ 384
10.3.2 DMA Destination Address Registers (DAR) .................................................... 384
10.3.3 DMA Transfer Count Registers (DMATCR) ................................................... 385
10.3.4 DMA Channel Control Registers (CHCR) ....................................................... 385
10.3.5 DMA Reload Source Address Registers (RSAR) ............................................. 396
10.3.6 DMA Reload Destination Address Registers (RDAR) ..................................... 396
10.3.7 DMA Reload Transfer Count Registers (RDMATCR) .................................... 397
10.3.8 DMA Operation Register (DMAOR) ............................................................... 398
10.3.9 DMA Extension Resource Selectors 0 to 7 (DMARS0 to DMARS7) .............. 402
10.4 Operation .......................................................................................................................... 408
10.4.1 Transfer Flow .................................................................................................... 408
10.4.2 DMA Transfer Requests ................................................................................... 410
10.4.3 Channel Priority ................................................................................................ 417
10.4.4 DMA Transfer Types ........................................................................................ 417
10.4.5 Number of Bus Cycles and DREQ Pin Sampling Timing ................................ 426
10.5 Usage Notes ...................................................................................................................... 430
10.5.1 Timing of DACK and TEND Outputs .............................................................. 430
10.5.2 Notes on Using Flag Bits .................................................................................. 430
Section 11 Multi-Function Timer Pulse Unit 2 ................................................. 431
11.1 Features ............................................................................................................................. 431
11.2 Input/Output Pins .............................................................................................................. 436