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Section 9 Bus State Controller
Page 240 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
10, 9 DPRTY[1:0] 00 R/W DMA Burst Transfer Priority
Specify the priority for a refresh request/bus
mastership request during DMA burst transfer.
00: Accepts a refresh request and bus mastership
request during DMA burst transfer.
01: Accepts a refresh request but does not accept a
bus mastership request during DMA burst
transfer.
10: Accepts neither a refresh request nor a bus
mastership request during DMA burst transfer.
11: Reserved (setting prohibited)
8 to 6 DMAIW[2:0] 000 R/W Wait states between access cycles when DMA single
address transfer is performed.
Specify the number of idle cycles to be inserted after
an access to an external device with DACK when
DMA single address transfer is performed. The
method of inserting idle cycles depends on the
contents of DMAIWA.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted