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Section 22 Renesas SPDIF Interface
Page 1152 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
22.3 Functional Block Diagram
Receiver
control
Receiver
data
handling
Clock
recovery and
frame counter
Oversampling clock
SPDIF_OUT
SPDIF_IN
Peripheral bus
Transmitter
data
handling
Parity
generator
Transmitter
control
Frame
counter
Parity
check
BMC decode
and preamble
detection
BMC and
preamble
encoding
AUDIO_X1
AUDIO_X2
AUDIO_CLK
Figure 22.2 Functional Block Diagram