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Section 9 Bus State Controller
R01UH0134EJ0400 Rev. 4.00 Page 229 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Section 9 Bus State Controller
The bus state controller outputs control signals for various types of memory and external devices
that are connected to the external address space. The functions of this module enable this LSI to
connect directly with SRAM, SDRAM, and other memory storage devices, and external devices.
9.1 Features
1. External address space
A maximum of 64 Mbytes for each of areas CS0 to CS6.
Can specify the normal space interface, SRAM interface with byte selection, burst ROM
(clocked synchronous or asynchronous), MPX-I/O, SDRAM memory type, and PCMCIA
interface for each address space.
Data bus width for CS0 space is 16 bits. Can select the data bus width (8 or 16 bits) for
each of address spaces CS1 to CS6.
Controls insertion of wait cycles for each address space.
Controls insertion of wait cycles for each read access and write access.
Can set independent idle cycles during the continuous access for five cases: read-write (in
same space/different spaces), read-read (in same space/different spaces), the first cycle is a
write access.
2. Normal space interface
Supports the interface that can directly connect to the SRAM.
3. Burst ROM interface (clocked asynchronous)
High-speed access to the ROM that has the page mode function.
4. MPX-I/O interface
Can directly connect to a peripheral LSI that needs an address/data multiplexing.
5. SDRAM interface
Can set the SDRAM in up to two areas.
Multiplex output for row address/column address.
Efficient access by single read/single write.
High-speed access in bank-active mode.
Supports an auto-refresh and self-refresh.
Supports low-frequency and power-down modes.
Issues MRS and EMRS commands.