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Section 27 Video Display Controller 3
Page 1566 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
27.7 Register Descriptions
Tables 27.7 to 27.10 show the register configuration.
Table 27.7 Register Configuration in Video Receiving and Supplying Blocks
Register Name Abbreviation R/W Initial Value Address Access Size
Video operating mode
register
VIDEO_MODE R/W H'0000 0000 H'FFFF 2000 32, 16, 8
Video interrupt control
register
VIDEO_INT_CNT R/W H'0000 0000 H'FFFF 2004 32, 16, 8
Video input timing control
register
VIDEO_TIM_CNT R/W H'0000 0000 H'FFFF 2008 32, 16, 8
Valid video size register VIDEO_SIZE R/W H'00F0 02D0 H'FFFF 2100 32, 16, 8
Vertical valid video start
position register
VIDEO_VSTART R/W H'0010 0117 H'FFFF 2104 32, 16, 8
Horizontal valid video start
position register
VIDEO_HSTART R/W H'0000 0114 H'FFFF 2108 32, 16, 8
Timing control register 1 for
vertical sync signal for
video
VIDEO_VSYNC_TIM1 R/W H'0000 0000 H'FFFF 210C 32, 16, 8
Video storing field count
register
VIDEO_SAVE_NUM R/W H'0000 0000 H'FFFF 2110 32, 16, 8
Video scaling and
correction register
VIDEO_IMAGE_CNT R/W H'8080 0300 H'FFFF 2114 32, 16, 8
Video base address
register
VIDEO_BASEADR R/W H'0000 0000 H'FFFF 2118 32, 16, 8
Video line offset register VIDEO_LINE_OFFSET R/W H'0000 0000 H'FFFF 211C 32, 16, 8
Video field offset register VIDEO_FIELD_OFFSET R/W H'0000 0000 H'FFFF 2120 32, 16, 8
Video line buffer count
register
VIDEO_LINEBUFF_NUM R/W H'0000 0000 H'FFFF 2124 32, 16, 8
Video display and recording
size register
VIDEO_DISP_SIZE R/W H'00F0 0168 H'FFFF 2128 32, 16, 8
Horizontal video display
position register
VIDEO_DISP_HSTART R/W H'0000 0000 H'FFFF 212C 32, 16, 8
Note: While operations of the video receiving and supplying blocks are in progress, writing to the
registers in video receiving and supplying blocks except the operation enable bits is
prohibited.