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Section 17 I
2
C Bus Interface 3
R01UH0134EJ0400 Rev. 4.00 Page 887 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
17.6 Bit Synchronous Circuit
In master mode, this module has a possibility that high level period may be short in the two states
described below.
When SCL is driven to low by the slave device
When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pull-
up resistance)
Therefore, it monitors SCL and communicates by bit with synchronization.
Figure 17.22 shows the timing of the bit synchronous circuit and table 17.5 shows the time when
the SCL output changes from low to Hi-Z then SCL is monitored.