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Section 10 Direct Memory Access Controller
R01UH0134EJ0400 Rev. 4.00 Page 427 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
CKIO
DREQ
(Overrun 0 at
high level)
DACK
(Active-high)
Bus cycle
1st acceptance
CPU
CPUCPU
DMA
CKIO
DREQ
(Overrun 1 at
high level)
DACK
(Active-high)
Bus cycle
2nd acceptance
CPU CPUCPU DMA
Acceptance
start
Acceptance
start
2nd acceptance
1st acceptance
Non sensitive period
Non sensitive period
Figure 10.12 Example of DREQ Input Detection in Cycle Steal Mode Level Detection
CKIO
DREQ
(Rising)
DACK
(Active-high)
Bus cycle
Burst acceptance
Non sensitive period
CPU CPU DMA
DMA
Figure 10.13 Example of DREQ Input Detection in Burst Mode Edge Detection