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Section 38 States and Handling of Pins
Page 2056 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
2. After the chip has shifted to the power-on reset state from deep standby mode by the
input on any of pins NMI, PC8 to PC5, PJ3, and PJ1, the pins retain the state until the
IOKEEP bit in the deep standby cancel source flag register (DSFR) is cleared (see
section 33, Power-Down Modes).
3. The EBUSKEEPE bit in deep standby control register (DSTCR) (see section 33, Power-
Down Modes).
4. This LSI enters the power-on reset state for a certain period after recovery from deep
standby control mode (see section 33, Power-Down Modes).
5. Depends on the setting of the RCKSEL bit in the realtime clock control register 5
(RCR5) (see section 14, Realtime Clock).
6. When pins for the connection with a crystal resonator are not used, the input pins
(EXTAL, RTC_X1, AUDIO_X1, and USB_X1) must be fixed (pull-up/down resistor,
power supply, or ground.) and the output pins (XTAL, RTC_X2, AUDIO_X2, and
USB_X2) must be open.
7. Depends on the setting of the CKOEN bit in the frequency control register (FRQCR) of
the clock pulse generator (see section 5, Clock Pulse Generator).
8. Depends on the setting of the AXTALE bit in the software reset control register
(SWRSTCR) (see section 33, Power-Down Modes).
9. Depends on the setting of the HIZ bit in the standby control register 3 (STBCR3) (see
section 33, Power-Down Modes).
10. Depends on the setting of the HIZMEM bit in the common control register (CMNCR) of
the bus state controller (see section 9, Bus State Controller).
11. Depends on the setting of the HIZCNT bit in the common control register (CMNCR) of
the bus state controller (see section 9, Bus State Controller).
12. Depends on the setting of the corresponding bit in the deep standby cancel source
select register (DSSSR) (see section 33, Power-Down Modes).
13. Depends on the setting of the RTCEN bit in the realtime clock control register 2 (RCR2)
(see section 14, Realtime Clock).
14. Z when the TAP controller of the user debugging interface is neither the Shift-DR nor
Shift-IR state.
15. These are the pin states in product chip mode (ASEMD H). See the Emulation
Manual for the pin states in ASE mode (ASEMD L).
16. When this is an output, the output is fixed to either the High or Low level. There is no
oscillation.