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Section 20 Controller Area Network
R01UH0134EJ0400 Rev. 4.00 Page 1015 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
TSEG2: TSG2 + 1
The Bit Rate Calculation is:
Bit Rate =
f
clk
2 × (BRP + 1) × (TSEG1 + TSEG2 + 1)
Where BRP is given by the register value and TSEG1 and TSEG2 are derived values from TSG1
and TSG2 register values. The '+1' in the above formula is for the Sync-Seg which duration is 1
time quanta.
f
CLK
= Peripheral Clock
BCR Setting Constraints
TSEG1min > TSEG2 SJWmax (SJW = 1 to 4)
8 < TSEG1 + TSEG2 + 1 < 25 time quanta (TSEG1 + TSEG2 + 1 = 7 is not allowed)
TSEG2 > 2
These constraints allow the setting range shown in the table below for TSEG1 and TSEG2 in the
Bit Configuration Register. The number in the table shows possible setting of SJW. "No" shows
that there is no allowed combination of TSEG1 and TSEG2.