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Section 26 USB 2.0 Host/Function Module
R01UH0134EJ0400 Rev. 4.00 Page 1499 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
(13) ATTCH Interrupt
The ATTCH interrupt is generated when J-state or K-state of the full-speed or low-speed level
signal is detected on the USB port for 2.5 s in host controller mode. To be more specific, the
ATTCH interrupt is detected on any of the following conditions.
(a) When K-state, SE0, or SE1 changes to J-state, and J-state continues 2.5 s.
(b) When J-state, SE0, or SE1 changes to K-state, and K-state continues 2.5 s.
(14) EOFERR Interrupt
The EOFERR interrupt is generated when it is detected that communication is not completed at
the EOF2 timing prescribed by USB Specification 2.0.
After detecting the EOFERR interrupt, this module controls hardware as described below
(irrespective of the set value of the corresponding interrupt enable bit). Terminate all the pipes in
which communications are currently carried out for the pertinent port and perform re-enumeration
of the pertinent port.
(a) Modifies the UACT bit for the port in which an EOFERR interrupt has been detected to 0.
(b) Puts the port in which an EOFERR interrupt has been generated into the idle state.
26.4.3 Pipe Control
Table 26.17 lists the pipe setting items of this module. With USB data transfer, data transmission
has to be carried out using the logic pipe called the endpoint. This module has ten pipes that are
used for data transfer.
Settings should be entered for each of the pipes in conjunction with the specifications of the
system.