Renesas R5S72621 Doll User Manual


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Section 25 NAND Flash Memory Controller
Page 1288 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
(3) Sectors and Control Codes
A sector is the basic unit of access and comprised of 512-byte data and 16-byte control code
fields. The control code field includes 8-byte ECC when the 3-symbol ECC circuit is used, and
10-byte ECC when the 4-symbol ECC circuit is used.
The position of the ECC in the control code field can be specified in 4-byte units when the 3-
symbol ECC circuit is used, and in 1-byte units when the 4-symbol ECC circuit is used.
User information can be written to the part of the control code field where ECC is not placed.
(4) 3-Symbol ECC
64 bits (8 bytes) of ECC is added to a sector, which consists of 512-byte data + 0/4/8-byte
control code.
Error correction and detection is up to three errors (30 bits at maximum) at random positions.
In a write operation, ECC is generated for the data and control code preceding the ECC. The
control code following the ECC is not considered.
In a read operation, an ECC error is checked for data and control code preceding the ECC. The
ECC on the control code in the FIFO are the results of checking replaced by the ECC circuit,
not the ECC read from flash memory.
Error correction is not performed even when an ECC error occurs. Error corrections must be
performed by software.
(5) 4-Symbol ECC
80 bits (10 bytes) of ECC is added to a sector, which consists of 512-byte data + 1-to 6-byte
control code.
Error correction and detection is up to four errors (40 bits at maximum) at random positions.
In a write operation, ECC is generated for the data and control code preceding the ECC. The
control code following the ECC is not considered.
In a read operation, an ECC error is checked for data and control code preceding the ECC. The
ECC on the control code in the FIFO are the results of checking replaced by the ECC circuit,
not the ECC read from flash memory.
The 4-symbol ECC circuit of this module has the capability of error correction pattern
generation by hardware, which is executed on a sector-by-sector basis.
In the error correction by hardware, addresses indicating the error positions and an error
pattern for correcting the errors are output. Data replacement must be performed by software.