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Section 35 Motor Control PWM Timer
Page 1842 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
35.5 Operation
35.5.1 PWM Operation
PWM waveforms are output from pins PWM1A to PWM1H and PWM2A to PWM2H as shown
in figure 35.7.
(1) Initial Settings
Set the PWM output polarity in PWPR_n; select the clock to be input to PWCNT_n with the
CKS2 to CKS0 bits in PWCRn; set the PWM conversion cycle in PWCYR_n; and set the first
frame of data in PWBFR_nA, PWBFR_nC, PWBFR_nE, and PWBFR_nG.
(2) Activation
When the CST bit in PWCR_n is set to 1, PWCNT_n starts counting up. On compare match
between PWCNT_n and PWCYR_n, data is transferred from the buffer register to the duty
register and the CMF bit in PWCR_n is set to 1. At the same time, if the IE bit in PWCR_n has
been set to 1, an interrupt can be requested or the direct memory access controller can be
activated.
(3) Waveform Output
The PWM outputs selected by the OTS bits in PWDTR_nA, PWDTR_nC, PWDTR_nE, and
PWDTR_nG go high when a compare match occurs between PWCNT_n and PWCYR_n. The
PWM outputs not selected by the OTS bit are low. When a compare match occurs between
PWCNT_n and PWDTR_nA, PWDTR_nC, PWDTR_nE, or PWDTR_nG, the corresponding
PWM output goes low. If the corresponding bit in PWPR_n is set to 1, the output is inverted.
PWBFRA
PWCYR
PWMA
PWDTRA
PWMB
OTS (PWDTRA) = 1OTS (PWDTRA) = 0OTS (PWDTRA) = 1OTS (PWDTRA) = 0
Figure 35.7 PWM Operation