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Section 21 IEBus
TM
Controller
Page 1114 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
21.3.10 IEBus Reception Master Address Register 2 (IEMA2)
IEMA2 indicates the upper eight bits of the communications destination master unit address in
slave/broadcast reception. This register is enabled when slave/broadcast reception starts, and the
contents are changed at the time of setting the RXS flag in IERSR.
If a broadcast receive error interrupt is selected with the DEE bit in IECTR and the receive buffer
is not in the receive enabled state at control field reception, a receive error interrupt is generated
and the upper eight bits of the master address are stored in IEMA2. This register cannot be
modified.
76543210
00000000
RRRRRRRR
Bit:
Initial value:
R/W:
IMAU8
Bit Bit Name
Initial
Value R/W Description
7 to 0 IMAU8 All 0 R Upper Eight Bits of IEBus Reception Master Address
Indicates the upper eight bits of the communications
destination master unit address in slave/broadcast
reception. This register is enabled when
slave/broadcast reception starts, and the contents are
changed at the time of setting the RXS flag. If a
broadcast receive error interrupt is selected by the DEE
bit in IECTR and the receive buffer is not in the receive
enabled state at control field reception, a receive error
interrupt is generated and the upper eight bits of the
master address are stored in IEMA2.