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Section 10 Direct Memory Access Controller
R01UH0134EJ0400 Rev. 4.00 Page 395 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
0 DE 0 R/W DMA Enable
Enables or disables the DMA transfer. In auto request
mode, DMA transfer starts by setting the DE bit and
DME bit in DMAOR to 1. In this case, all of the bits TE,
NMIF in DMAOR, and AE must be 0. In an external
request or peripheral module request, DMA transfer
starts if DMA transfer request is generated by the
devices or peripheral modules after setting the bits DE
and DME to 1. If the DREQ signal is detected by
low/high level in external request mode, or in
peripheral module request mode, the NMIF bit and the
AE bit must be 0 if the TEMASK bit is 1. If the
TEMASK bit is 0, the TE bit must also be 0. If the
DREQ signal is detected by a rising/falling edge in
external request mode, all of the bits TE, NMIF, and
AE must be 0 as in the case of auto request mode.
Clearing the DE bit to 0 can terminate the DMA
transfer.
0: DMA transfer disabled
1: DMA transfer enabled
Notes: 1. Only CHCR_0 can be used in the SH7262 Group.
2. Channels 1 to 15 can be used in the SH7262 Group.
3. Only 0 can be written to clear the flag after 1 is read.
4. If the flag is read at the same timing it is set to 1, the read data will be 0, but the internal
state may be the same as reading 1. Therefore, if 0 is written to the flag, the flag will be
cleared to 0 because the internal state is the same as when writing 0 after reading 1.
For details, refer to section 10.5.2, Notes on Using Flag Bits.