Filter
Top Products
Section 2 CPU
R01UH0134EJ0400 Rev. 4.00 Page 65 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
2.3.3 Instruction Format
The instruction formats and the meaning of source and destination operands are described below.
The meaning of the operand depends on the instruction code. The symbols used are as follows:
xxxx: Instruction code
mmmm: Source register
nnnn: Destination register
iiii: Immediate data
dddd: Displacement
Table 2.9 Instruction Formats
Instruction Formats
Source
Operand
Destination
Operand
Example
0 format
xxxx xxxx xxxxxxxx
15 0
NOP
n format
xxxx xxxx xxxxnnnn
15 0
nnnn: Register
direct
MOVT Rn
Control register or
system register
nnnn: Register
direct
STS MACH,Rn
R0 (Register direct) nnnn: Register
direct
DIVU R0,Rn
Control register or
system register
nnnn: Register
indirect with pre-
decrement
STC.L SR,@-Rn
mmmm: Register
direct
R15 (Register
indirect with pre-
decrement)
MOVMU.L
Rm,@-R15
R15 (Register
indirect with post-
increment)
nnnn: Register
direct
MOVMU.L
@R15+,Rn
R0 (Register direct) nnnn: (Register
indirect with post-
increment)
MOV.L R0,@Rn+