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Section 22 Renesas SPDIF Interface
R01UH0134EJ0400 Rev. 4.00 Page 1177 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
22.7.13 Receiver Channel 1 Status Register (RLCS)
The channel status is stored starting at the register's LSB in a way that subframe 1 received from
the beginning of the block is stored. For the contents of the channel status register, refer to the
IEC-60958 standard.
31 30 29 28 27 26 25 24
--000
- - CLAC[1:0]
000
RRRRRRRR
CHNO[3:0]
FS[3:0]
23 22 21 20 19 18 17
16
00000000
RRRRRRRR
SRCNO[3:0]
15 14 13 12 11 10 9
8
00000
CATCD[7:0]
000
RRRRRRRR
7654321
0
00000
- - CTL[4:0]
000
RRRRRRRR
-
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
31, 30 R Reserved
29, 28 CLAC[1:0] All 0 R Clock Accuracy
00: Level 2
01: Level 1
10: Level 3
11: Reserved
27 to 24 FS[3:0] All 0 R Sample Frequency (FS)
0000: 44.1 kHz
0010: 48 kHz
0011: 32 kHz