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Page xxx of xl R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
Section 24 A/D Converter ............................................................................... 1259
24.1 Features ........................................................................................................................... 1259
24.2 Input/Output Pins ............................................................................................................ 1261
24.3 Register Descriptions ...................................................................................................... 1262
24.3.1 A/D Data Registers A to H (ADDRA to ADDRH) ........................................ 1263
24.3.2 A/D Control/Status Register (ADCSR) .......................................................... 1264
24.4 Operation ........................................................................................................................ 1268
24.4.1 Single Mode .................................................................................................... 1268
24.4.2 Multi Mode ..................................................................................................... 1271
24.4.3 Scan Mode ...................................................................................................... 1273
24.4.4 A/D Converter Activation by External Trigger or
Multi-Function Timer Pulse Unit 2 ................................................................. 1276
24.4.5 Input Sampling and A/D Conversion Time .................................................... 1276
24.4.6 External Trigger Input Timing ........................................................................ 1279
24.5 Interrupt Sources and DMA Transfer Request ............................................................... 1280
24.6 Definitions of A/D Conversion Accuracy ....................................................................... 1281
24.7 Usage Notes .................................................................................................................... 1282
24.7.1 Module Standby Mode Setting ....................................................................... 1282
24.7.2 Setting Analog Input Voltage ......................................................................... 1282
24.7.3 Notes on Board Design ................................................................................... 1282
24.7.4 Processing of Analog Input Pins ..................................................................... 1283
24.7.5 Permissible Signal Source Impedance ............................................................ 1284
24.7.6 Influences on Absolute Precision .................................................................... 1285
24.7.7 Note on Usage in Scan Mode and Multi Mode ............................................... 1285
Section 25 NAND Flash Memory Controller .................................................. 1287
25.1 Features ........................................................................................................................... 1287
25.2 Input/Output Pins ............................................................................................................ 1291
25.3 Register Descriptions ...................................................................................................... 1292
25.3.1 Common Control Register (FLCMNCR) ....................................................... 1293
25.3.2 Command Control Register (FLCMDCR) ...................................................... 1297
25.3.3 Command Code Register (FLCMCDR) ......................................................... 1300
25.3.4 Address Register (FLADR) ............................................................................ 1301
25.3.5 Address Register 2 (FLADR2) ....................................................................... 1303
25.3.6 Data Counter Register (FLDTCNTR)............................................................. 1304
25.3.7 Data Register (FLDATAR) ............................................................................ 1305
25.3.8 Interrupt DMA Control Register (FLINTDMACR) ....................................... 1306
25.3.9 Ready Busy Timeout Setting Register (FLBSYTMR) ................................... 1311
25.3.10 Ready Busy Timeout Counter (FLBSYCNT) ................................................. 1312
25.3.11 Data FIFO Register (FLDTFIFO) ................................................................... 1313