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Section 19 Serial I/O with FIFO
Page 952 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
8 RDREQ 0 R Receive Data Transfer Request
0: Indicates that the size of valid space in the receive
FIFO is less than the size specified by the RFWM bit in
SIFCTR.
1: Indicates that the size of valid space in the receive
FIFO is equal to or greater than the size specified by
the RFWM bit in SIFCTR.
A receive data transfer request is issued when the valid
space in the receive FIFO exceeds the size specified by
the RFWM bit in SIFCTR.
When receive data is transferred through the direct
memory access controller, this bit is always cleared by an
access of the direct memory access controller. If the
condition for setting this bit is satisfied after the access of
the direct memory access controller, this module again
sets this bit to 1.
This bit is valid when the RXE bit in SICTR is 1.
If the size of valid space in the receive FIFO is less
than the size specified by the RFWM bit in SIFCTR,
this module clears this bit.
7 to 5 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
4 FSERR 0 R/W Frame Synchronization Error
0: Indicates that no frame synchronization error occurs
1: Indicates that a frame synchronization error occurs
A frame synchronization error occurs when the next
frame synchronization timing appears before the previous
data transfer has been completed.
If a frame synchronization error occurs, this module
performs transmission or reception for slots that can be
transferred.
This bit is valid when the TXE or RXE bit in SICTR
is 1.
When this bit is set to 1, it is cleared to 0 by this
module. Writing 0 to this bit is invalid.