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Section 20 Controller Area Network
Page 984 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Important: LongWord (32-bit) accesses are converted into two consecutive word (16-bit)
accesses by the bus interface.
Micro Processor Interface (MPI)
The MPI allows communication between the Renesas CPU and this module’s
registers/mailboxes to control the memory interface. It also contains the Wakeup Control logic
that detects the CAN bus activities and notifies the MPI and the other parts of this module so
that this module can automatically exit the Sleep mode.
It contains registers such as MCR, IRR, GSR and IMR.
Mailbox
The Mailboxes consists of RAM configured as message buffers and registers. There are 32
Mailboxes, and each mailbox has the following information.
<RAM>
CAN message control (identifier, rtr, ide,etc)
CAN message data (for CAN Data frames)
Local Acceptance Filter Mask for reception
<Registers>
CAN message control (dlc)
Time Stamp for message reception/transmission
3-bit wide Mailbox Configuration, Disable Automatic Re-Transmission bit, Auto-
Transmission for Remote Request bit, New Message Control bit
Tx-Trigger Time
Mailbox Control
The Mailbox Control handles the following functions.
For received messages, compare the IDs and generate appropriate RAM addresses/data to
store messages from the CAN Interface into the Mailbox and set/clear appropriate registers
accordingly.
To transmit event-triggered messages, run the internal arbitration to pick the correct
priority message, and load the message from the Mailbox into the Tx-buffer of the CAN
Interface and set/clear appropriate registers accordingly. In the case of time-triggered
transmission, compare match of Tx-Trigger time invoke loading the messages.
Arbitrates Mailbox accesses between the CPU and the Mailbox Control.
Contains registers such as TXPR, TXCR, TXACK, ABACK, RXPR, RFPR, UMSR and
MBIMR.