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Section 24 A/D Converter
R01UH0134EJ0400 Rev. 4.00 Page 1267 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
2 to 0 CH[2:0] 000 R/W Channel Select
These bits and the MDS bits in ADCSR select the
analog input channels.
MDS = 0xx
MDS = 100 or
MDS = 110
MDS = 101 or
MDS = 111
000: AN0 000: AN0 000: AN0
001: AN1 001: AN0, AN1 001: AN0, AN1
010: AN2 010: AN0 to AN2 010: AN0 to AN2
011: AN3 011: AN0 to AN3 011: AN0 to AN3
100: AN4*
3
100: AN4*
3
100: AN0 to AN4*
3
101: AN5*
3
101: AN4, AN5*
3
101: AN0 to AN5*
3
110: AN6*
3
110: AN4 to AN6*
3
110: AN0 to AN6*
3
111: AN7*
3
111: AN4 to AN7*
3
111: AN0 to AN7*
3
[Legend]
x: Don't care
Notes: 1. Only 0 can be written to clear the flag after 1 is read.
Please note that ADF flag becomes "0" in the following cases, too.
(1) Reading the state of ADF = 1 with CPU.
(2) Clearing ADF flag by having read ADDR with DMAC
(3) Set of ADF flag according to A/D conversion end
(4) Writing 0 in the ADF flag with CPU
2. Set the A/D conversion time to minimum or more values to meet the absolute accuracy
of the A/D conversion characteristics.
3. Settings prohibited in the SH7262 Group.