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Section 11 Multi-Function Timer Pulse Unit 2
Page 502 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
11.3.27 Timer Buffer Transfer Set Register (TBTER)
TBTER is an 8-bit readable/writable register that enables or disables transfer from the buffer
registers* used in complementary PWM mode to the temporary registers and specifies whether to
link the transfer with interrupt skipping operation. This module has one TBTER.
Bit:
Initial value:
R/W:
7654321
0
00000000
RRRRRRR/WR/W
- - - - - - BTE[1:0]
Bit Bit Name
Initial
Value R/W Description
7 to 2 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
1, 0 BTE[1:0] 00 R/W These bits enable or disable transfer from the buffer
registers* used in complementary PWM mode to the
temporary registers and specify whether to link the
transfer with interrupt skipping operation.
For details, see table 11.40.
Note: * Applicable buffer registers:
TGRC_3, TGRD_3, TGRC_4, TGRD_4, and TCBR