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Section 27 Video Display Controller 3
Page 1570 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
27.7.1 Video Operating Mode Register (VIDEO_MODE)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
0000000000000000
R R R/W R/W R R R R R R R/W R/W R R R/W R/W
0000000000000000
R R/W R/W R/W R R R R R R R R/W R R R/W R/W
--
RGB565
INV_
CbCr
--
-
----
BURST_
MODE_
DISP
BURST_
MODE_
MAIN
--
ENDIAN
_DISP
ENDIAN
_MAIN
-
SEL_
EXSYNC
SEL_
656601
SEL_
525625
------
VIDEO_
MODE
--
VIDEO_
DISP_
EXE
VIDEO_
MAIN_
EXE
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
31, 30 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
29 RGB565 0 R/W Specifies the method of conversion from RGB888
to RGB565.
0: Converted by the operation described in section
27.6.1 (4), Conversion from RGB888 to
RGB565.
1: Lower bits are truncated.
28 INV_CbCr 0 R/W Specifies Cb and Cr inversion.
0: Normal operation
1: Inversion
27 to 22 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
21 BURST_MODE
_DISP
0 R/W Selects the mode of transfer through the IV2-BUS
in the video supplying block. Reading out from the
areas except the large-capacity on-chip RAM
requires this bit to be set to 0.
0: 16-byte burst transfer
1: 128-byte burst transfer