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Section 9 Bus State Controller
R01UH0134EJ0400 Rev. 4.00 Page 357 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Table 9.16 Conditions for Determining Number of Idle Cycles
No. Condition Description Range Note
[1] DMAIW[2:0] in
CMNCR
These bits specify the number of
idle cycles for DMA single address
transfer. This condition is effective
only for single address transfer and
generates idle cycles after the
access is completed.
0 to 12 When 0 is specified for the
number of idle cycles, the
DACK signal may be
asserted continuously. This
causes a discrepancy
between the number of
cycles detected by the device
with DACK and the direct
memory access controller
transfer count, resulting in a
malfunction.
[2] IW***[2:0] in
CSnBCR
These bits specify the number of
idle cycles for access other than
single address transfer. The
number of idle cycles can be
specified independently for each
combination of the previous and
next cycles. For example, in the
case where reading CS1 space
followed by reading other CS
space, the bits IWRRD[2:0] in
CS1BCR should be set to B'100 to
specify six or more idle cycles. This
condition is effective only for access
cycles other than single address
transfer and generates idle cycles
after the access is completed.
0 to 12 Do not set 0 for the number
of idle cycles between
memory types which are not
allowed to be accessed
successively.
[3] SDRAM-related
bits in
CSnWCR
These bits specify precharge
completion and startup wait cycles
and idle cycles between commands
for SDRAM access. This condition
is effective only for SDRAM access
and generates idle cycles after the
access is completed
0 to 3 Specify these bits in
accordance with the
specification of the target
SDRAM.