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Section 16 Renesas Serial Peripheral Interface
Page 784 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
16.3.3 Pin Control Register (SPPCR)
SPPCR sets the modes of the pins. If the contents of this register are changed while the function of
this module is enabled by setting the SPE bit in the control register (SPCR) to 1, subsequent
operations cannot be guaranteed.
76543210
Bit:
Initial value:
R/W:
00000000
R R R/W R/W R R R R/W
⎯⎯
MOIFE MOIFV
⎯⎯⎯
SPLP
Bit Bit Name
Initial
Value R/W Description
7, 6 All 0 R Reserved
The write value should always be 0. Otherwise,
operation cannot be guaranteed.
5 MOIFE 0 R/W MOSI Idle Value Fixing Enable
Fixes the MOSI output value when this module in
master mode is in an SSL negation period (including
the SSL retention period during a burst transfer).
When MOIFE is 0, this module outputs the last data
from the previous serial transfer during the SSL
negation period. When MOIFE is 1, this module
outputs the fixed value set in the MOIFV bit to the
MOSI bit.
0: MOSI output value equals final data from previous
transfer
1: MOSI output value equals the value set in the
MOIFV bit
4 MOIFV 0 R/W MOSI Idle Fixed Value
If the MOIFE bit is 1 in master mode, this module,
according to MOIFV bit settings, determines the
MOSI signal value during the SSL negation period
(including the SSL retention period during a burst
transfer).
0: MOSI Idle fixed value equals 0
1: MOSI Idle fixed value equals 1
3 to 1 All 0 R Reserved
The write value should always be 0. Otherwise,
operation cannot be guaranteed.