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Section 9 Bus State Controller
R01UH0134EJ0400 Rev. 4.00 Page 265 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
17, 16 BW[1:0] 00 R/W Number of Burst Wait Cycles
Specify the number of wait cycles to be inserted
between the second or subsequent access cycles in
burst access.
00: No cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles
15 to 11 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
10 to 7 W[3:0] 1010 R/W Number of Access Wait Cycles
Specify the number of wait cycles to be inserted in the
first access cycle.
0000: No cycle
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (setting prohibited)
1110: Reserved (setting prohibited)
1111: Reserved (setting prohibited)