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Section 27 Video Display Controller 3
Page 1636 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
27.9 Interrupt Requests
This module issues four types of interrupt request: VSYNC cycle fluctuation detection, buffer
error, field write completion, and line interrupt requests.
Table 27.27 is a list of interrupt requests.
Table 27.27 List of Interrupt Requests
Interrupt Request Symbol Interrupt Request Condition
VSYNC cycle
fluctuation detection
VIVSYNCJ (VIDEO_INT_CNT.V_PERIOD=1)&(VIDEO_INT_CNT.INT_V_EN=1)
Buffer error VBUFERR (VIDEO_INT_CNT.UNDER_FLOW=1)&(VIDEO_INT_CNT.INT_UF_EN=1)|
(VIDEO_INT_CNT.OVER_FLOW=1)&(VIDEO_INT_CNT.INT_OF_EN=1)|
(GRCINTCNT1.UNDER_FLOW=1)&(GRCINTCNT1.INT_UF_EN=1)|
(GRCINTCNT2.UNDER_FLOW=1)&(GRCINTCNT2.INT_UF_EN=1)
Field write
completion
VIFIELDE (VIDEO_INT_CNT.F_END=1)&(VIDEO_INT_CNT.INT_F_EN=1)
Line interrupt VOLINE (SGINTCNT.LINE_STATUS=1)&(SGINTCNT.INT_LINE_EN=1)
When a condition shown in table 27.27 is evaluated to 1, this module issues an interrupt request.
27.10 Usage Note
27.10.1 The Procedure of Disabling the Video Receiving Block Operation
When disabling the Video receiving block operation, please follow the procedure given below.
1. Unselect the DV_CLK function of PF8 mode in the control register (PFCR2) of general
purpose I/O ports. (select the PF8 function)
2. Clear the VIDEO_MAIN_EXE bit in VIDEO_MODE register to 0.
3. Halt the clock to video display controller 3 by the standby control register (STBCR7) of
power-down modes.
4. Select the DV_CLK function of PF8 mode in the control register (PFCR2) of general purpose
I/O ports.
5. Supply the clock to video display controller 3 by the standby control register (STBCR7) of
power-down modes.