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R01UH0134EJ0400 Rev. 4.00 Page 2099 of 2108
Sep 24, 2014
E
ECC correction ..................................... 1248
ECC error check ................................... 1332
EDC checking ....................................... 1249
Effective address calculation .................... 60
Electrical characteristics ....................... 1961
Endian ..................................................... 291
Endian conversion for data in
the input stream .................................... 1242
Equation for getting SCBRR value ......... 732
Error detection function .......................... 827
Example of time triggered system ........ 1069
Exception handling ................................. 131
Exception handling state ........................... 93
Exception handling vector table ............. 134
Exception source generation
immediately after delayed branch
instruction ............................................... 151
Exceptions triggered by instructions ....... 147
External request mode ............................ 410
External trigger input timing ................ 1279
F
Features of this LSI ..................................... 1
Floating point operation instructions ...... 150
Floating-point operation instructions ........ 87
Floating-point ranges ................................ 98
Floating-point registers ........................... 101
Floating-point unit (FPU) ......................... 95
Format of double-precision
floating-point number ............................... 96
Format of single-precision
foating-point number ................................ 96
FPU exception sources ........................... 106
FPU-related CPU instructions .................. 89
Full-scale error ...................................... 1281
G
General illegal instructions ..................... 149
General purpose I/O ports timing .......... 2041
General registers ....................................... 49
Global base register (GBR) ....................... 51
H
Halt mode .............................................. 1055
I
I
2
C bus format ......................................... 868
I
2
C bus interface 3 ................................... 849
I
2
C bus interface 3 timing ..................... 2023
IBUF interrupt ....................................... 1255
ID reorder .............................................. 1005
IEBus bit format .................................... 1099
IEBus communications protocol ........... 1084
IEBus controller ................................ 1083
IERR interrupt ....................................... 1255
Immediate data .......................................... 58
Immediate data accessing .......................... 58
Immediate data format .............................. 55
Influences on absolute precision ........... 1285
Initial values of control registers ............... 53
Initial values of general registers .............. 53
Initial values of system registers ............... 53
Instruction features .................................... 56
Instruction format ...................................... 65
Instruction set ............................................ 69
Integer division instructions .................... 149
Internal arbitration for transmission ...... 1059
Interrupt controller .................................. 157
Interrupt exception handling ................... 146
Interrupt exception handling vectors
and priorities ........................................... 178
Interrupt priority level ............................. 145
Interrupt response time ........................... 195
Interrupt sources...................................... 770