Filter
Top Products
Section 26 USB 2.0 Host/Function Module
Page 1482 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
(ii) For the pipe in the receiving direction:
When packet reception is completed successfully thus enabling the FIFO buffer to be read
when read-access from the CPU to the FIFO buffer for the pertinent pipe is disabled (when
the BSTS bit is read as 0).
The request trigger is not generated for the transaction in which DATA-PID disagreement
occurs.
In continuous transmission/reception mode, the request trigger is not generated when the
data is of the specified maximum packet size and the buffer has available space.
When a short packet is received, the request trigger is generated even if the FIFO buffer
has available space.
When the transaction counter is used, the request trigger is generated on receiving the
specified number of packets. In this case, the request trigger is generated even if the FIFO
buffer has available space.
When one FIFO buffer is read-enabled on completion of reading data from the other FIFO
buffer in double buffer mode.
The request trigger is not generated until completion of reading data from the currently-
read FIFO buffer plane even if reception by the other FIFO buffer is completed.
When the function controller function is selected, the BRDY interrupt is not generated in the
status stage of control transfers.
The PIPEBRDY interrupt status of the pertinent pipe can be cleared to 0 by writing 0 to the
corresponding PIPEBRDY interrupt status bit in the BRDYSTS register. In this case, 1s should be
written to the PIPEBRDY interrupt status bits for the other pipes.
Be sure to clear the BRDY status before accessing the FIFO buffer.