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Section 26 USB 2.0 Host/Function Module
R01UH0134EJ0400 Rev. 4.00 Page 1375 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
11, 10 MBW[1:0] 00 R/W FIFO Port Access Bit Width
Specifies the bit width for accessing the DnFIFO
port.
00: 8-bit width
01: 16-bit width
10: 32-bit width
11: Setting prohibited
Once reading data is started after setting these bits,
these bits should not be modified until all the data
has been read.
When the selected pipe is in the receiving direction,
set the CURPIPE and MBW bits simultaneously.
For details, see section 26.4.4, FIFO Buffer
Memory.
When the selected pipe is in the transmitting
direction, the bit width cannot be changed from the
8-bit width to the 16-/32-bit width or from the 16-bit
width to the 32-bit width while data is being written
to the buffer memory.
9 0 R Reserved
This bit is always read as 0. The write value should
always be 0.
8 BIGEND 0 R/W FIFO Port Endian Control
Specifies the byte endian for the DnFIFO port.
0: Little endian
1: Big endian
7 to 4 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.