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Section 17 I
2
C Bus Interface 3
R01UH0134EJ0400 Rev. 4.00 Page 853 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
17.3.1 I
2
C Bus Control Register 1 (ICCR1)
ICCR1 is an 8-bit readable/writable register that enables or disables the I
2
C bus interface 3,
controls transmission or reception, and selects master or slave mode, transmission or reception,
and transfer clock frequency in master mode.
76543210
00000000
R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
Initial value:
R/W:
ICE RCVD MST TRS CKS[3:0]
Bit Bit Name
Initial
Value R/W Description
7 ICE 0 R/W I
2
C Bus Interface 3 Enable
0: SCL and SDA output is disabled. (Input to SCL and
SDA is enabled.)
1: This bit is enabled for transfer operations. (SCL and
SDA pins are bus drive state.)
6 RCVD 0 R/W Reception Disable
Enables or disables the next operation when TRS is 0
and ICDRR is read.
0: Enables next reception
1: Disables next reception