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Section 9 Bus State Controller
Page 318 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
(4) Single Read
A read access ends in one cycle when data exists in a cache-disabled space and the data bus width
is larger than or equal to the access size. As the SDRAM is set to the burst read with the burst
length 1, only the required data is output. A read access that ends in one cycle is called single read.
Figure 9.17 shows the single read basic timing.
(Tap)Tr Tc1 TdeTd1
CKIO
A25 to A0
CSn
RD/WR
RAS
DQMx
D15 to D0
BS
DACKn*
2
A12/A11*
1
CAS
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.17 Basic Timing for Single Read (CAS Latency 1, Auto Pre-Charge)