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R01UH0134EJ0400 Rev. 4.00 Page xiii of xl
Sep 24, 2014
5.7.2 Oscillation Stabilizing Time of the PLL circuit ................................................ 128
5.8 Notes on Board Design ..................................................................................................... 129
5.8.1 Note on Using a PLL Oscillation Circuit .......................................................... 129
Section 6 Exception Handling ........................................................................... 131
6.1 Overview ........................................................................................................................... 131
6.1.1 Types of Exception Handling and Priority ........................................................ 131
6.1.2 Exception Handling Operations ........................................................................ 132
6.1.3 Exception Handling Vector Table ..................................................................... 134
6.2 Resets ................................................................................................................................ 137
6.2.1 Input/Output Pins .............................................................................................. 137
6.2.2 Types of Reset .................................................................................................. 137
6.2.3 Power-On Reset ................................................................................................ 139
6.2.4 Manual Reset .................................................................................................... 140
6.3 Address Errors .................................................................................................................. 142
6.3.1 Address Error Sources ...................................................................................... 142
6.3.2 Address Error Exception Handling ................................................................... 143
6.4 Register Bank Errors ......................................................................................................... 143
6.4.1 Register Bank Error Sources ............................................................................. 143
6.4.2 Register Bank Error Exception Handling ......................................................... 144
6.5 Interrupts ........................................................................................................................... 144
6.5.1 Interrupt Sources ............................................................................................... 144
6.5.2 Interrupt Priority Level ..................................................................................... 145
6.5.3 Interrupt Exception Handling ........................................................................... 146
6.6 Exceptions Triggered by Instructions ............................................................................... 147
6.6.1 Types of Exceptions Triggered by Instructions ................................................ 147
6.6.2 Trap Instructions ............................................................................................... 148
6.6.3 Slot Illegal Instructions ..................................................................................... 148
6.6.4 General Illegal Instructions ............................................................................... 149
6.6.5 Integer Division Exceptions .............................................................................. 149
6.6.6 FPU Exceptions ................................................................................................ 150
6.7 When Exception Sources Are Not Accepted .................................................................... 151
6.8 Stack Status after Exception Handling Ends ..................................................................... 151
6.9 Usage Notes ...................................................................................................................... 153
6.9.1 Value of Stack Pointer (SP) .............................................................................. 153
6.9.2 Value of Vector Base Register (VBR) .............................................................. 153
6.9.3 Address Errors Caused by Stacking of Address Error Exception Handling ..... 153
6.9.4 Interrupt Control via Modification of Interrupt Mask Bits ............................... 153
6.9.5 Note before Exception Handling Begins Running ............................................ 154