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Section 2 CPU
R01UH0134EJ0400 Rev. 4.00 Page 87 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
2.4.8 Floating-Point Operation Instructions
Table 2.17 Floating-Point Operation Instructions
Instruction Instruction Code Operation
Execu-
tion
Cycles T Bit
Compatibility
SH2E SH4
SH-2A/
SH2A-
FPU
FABS FRn 1111nnnn01011101 |FRn| FRn 1 Yes Yes Yes
FABS DRn 1111nnn001011101 |DRn| DRn 1 Yes Yes
FADD FRm, FRn 1111nnnnmmmm0000 FRn + FRm FRn 1 Yes Yes Yes
FADD DRm, DRn 1111nnn0mmm00000 DRn + DRm DRn 6 Yes Yes
FCMP/EQ FRm, FRn 1111nnnnmmmm0100 (FRn = FRm)? 1:0 T1 Com-
parison
result
Yes Yes Yes
FCMP/EQ DRm, DRn 1111nnn0mmm00100 (DRn = DRm)? 1:0 T2 Com-
parison
result
Yes Yes
FCMP/GT FRm, FRn 1111nnnnmmmm0101 (FRn > FRm)? 1:0 T1 Com-
parison
result
Yes Yes Yes
FCMP/GT DRm, DRn 1111nnn0mmm00101 (DRn > DRm)? 1:0 T2 Com-
parison
result
Yes Yes
FCNVDS DRm, FPUL 1111mmm010111101 (float) DRm FPUL 2 Yes Yes
FCNVSD FPUL, DRn 1111nnn010101101 (double) FPUL DRn 2 Yes Yes
FDIV FRm, FRn 1111nnnnmmmm0011 FRn/FRm FRn 10 Yes Yes Yes
FDIV DRm, DRn 1111nnn0mmm00011 DRn/DRm DRn 23 Yes Yes
FLDI0 FRn 1111nnnn10001101 0 00000000 FRn 1 Yes Yes Yes
FLDI1 FRn 1111nnnn10011101 0 3F800000 FRn 1 Yes Yes Yes
FLDS FRm, FPUL 1111mmmm00011101 FRm FPUL 1 Yes Yes Yes
FLOAT FPUL,FRn 1111nnnn00101101 (float)FPUL FRn 1 Yes Yes Yes
FLOAT FPUL,DRn 1111nnn000101101 (double)FPUL DRn 2 Yes Yes
FMAC FR0,FRm,FRn 1111nnnnmmmm1110 FR0 FRm+FRn
FRn
1 Yes Yes Yes
FMOV FRm, FRn 1111nnnnmmmm1100 FRm FRn 1 Yes Yes Yes
FMOV DRm, DRn 1111nnn0mmm01100 DRm DRn 2 Yes Yes