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Section 36 List of Registers
Page 1920 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Module Name
Register
Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0
Controller area
network
TXPR1_0 TXPR1[15] TXPR1[14] TXPR1[13] TXPR1[12] TXPR1[11] TXPR1[10] TXPR1[9] TXPR1[8]
TXPR1[7] TXPR1[6] TXPR1[5] TXPR1[4] TXPR1[3] TXPR1[2] TXPR1[1] TXPR1[0]
TXPR0_0 TXPR0[15] TXPR0[14] TXPR0[13] TXPR0[12] TXPR0[11] TXPR0[10] TXPR0[9] TXPR0[8]
TXPR0[7] TXPR0[6] TXPR0[5] TXPR0[4] TXPR0[3] TXPR0[2] TXPR0[1]
TXCR1_0 TXCR1[15] TXCR1[14] TXCR1[13] TXCR1[12] TXCR1[11] TXCR1[10] TXCR1[9] TXCR1[8]
TXCR1[7] TXCR1[6] TXCR1[5] TXCR1[4] TXCR1[3] TXCR1[2] TXCR1[1] TXCR1[0]
TXCR0_0 TXCR0[15] TXCR0[14] TXCR0[13] TXCR0[12] TXCR0[11] TXCR0[10] TXCR0[9] TXCR0[8]
TXCR0[7] TXCR0[6] TXCR0[5] TXCR0[4] TXCR0[3] TXCR0[2] TXCR0[1]
TXACK1_0 TXACK1[15] TXACK1[14] TXACK1[13] TXACK1[12] TXACK1[11] TXACK1[10] TXACK1[9] TXACK1[8]
TXACK1[7] TXACK1[6] TXACK1[5] TXACK1[4] TXACK1[3] TXACK1[2] TXACK1[1] TXACK1[0]
TXACK0_0 TXACK0[15] TXACK0[14] TXACK0[13] TXACK0[12] TXACK0[11] TXACK0[10] TXACK0[9] TXACK0[8]
TXACK0[7] TXACK0[6] TXACK0[5] TXACK0[4] TXACK0[3] TXACK0[2] TXACK0[1]
ABACK1_0 ABACK1[15] ABACK1[14] ABACK1[13] ABACK1[12] ABACK1[11] ABACK1[10] ABACK1[9] ABACK1[8]
ABACK1[7] ABACK1[6] ABACK1[5] ABACK1[4] ABACK1[3] ABACK1[2] ABACK1[1] ABACK1[0]
ABACK0_0 ABACK0[15] ABACK0[14] ABACK0[13] ABACK0[12] ABACK0[11] ABACK0[10] ABACK0[9] ABACK0[8]
ABACK0[7] ABACK0[6] ABACK0[5] ABACK0[4] ABACK0[3] ABACK0[2] ABACK0[1]
RXPR1_0 RXPR1[15] RXPR1[14] RXPR1[13] RXPR1[12] RXPR1[11] RXPR1[10] RXPR1[9] RXPR1[8]
RXPR1[7] RXPR1[6] RXPR1[5] RXPR1[4] RXPR1[3] RXPR1[2] RXPR1[1] RXPR1[0]
RXPR0_0 RXPR0[15] RXPR0[14] RXPR0[13] RXPR0[12] RXPR0[11] RXPR0[10] RXPR0[9] RXPR0[8]
RXPR0[7] RXPR0[6] RXPR0[5] RXPR0[4] RXPR0[3] RXPR0[2] RXPR0[1] RXPR0[0]
RFPR1_0 RFPR1[15] RFPR1[14] RFPR1[13] RFPR1[12] RFPR1[11] RFPR1[10] RFPR1[9] RFPR1[8]
RFPR1[7] RFPR1[6] RFPR1[5] RFPR1[4] RFPR1[3] RFPR1[2] RFPR1[1] RFPR1[0]
RFPR0_0 RFPR0[15] RFPR0[14] RFPR0[13] RFPR0[12] RFPR0[11] RFPR0[10] RFPR0[9] RFPR0[8]
RFPR0[7] RFPR0[6] RFPR0[5] RFPR0[4] RFPR0[3] RFPR0[2] RFPR0[1] RFPR0[0]
MBIMR1_0 MBIMR1[15] MBIMR1[14] MBIMR1[13] MBIMR1[12] MBIMR1[11] MBIMR1[10] MBIMR1[9] MBIMR1[8]
MBIMR1[7] MBIMR1[6] MBIMR1[5] MBIMR1[4] MBIMR1[3] MBIMR1[2] MBIMR1[1] MBIMR1[0]
MBIMR0_0 MBIMR0[15] MBIMR0[14] MBIMR0[13] MBIMR0[12] MBIMR0[11] MBIMR0[10] MBIMR0[9] MBIMR0[8]
MBIMR0[7] MBIMR0[6] MBIMR0[5] MBIMR0[4] MBIMR0[3] MBIMR0[2] MBIMR0[1] MBIMR0[0]
UMSR1_0 UMSR1[15] UMSR1[14] UMSR1[13] UMSR1[12] UMSR1[11] UMSR1[10] UMSR1[9] UMSR1[8]
UMSR1[7] UMSR1[6] UMSR1[5] UMSR1[4] UMSR1[3] UMSR1[2] UMSR1[1] UMSR1[0]