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Page xxvi of xl R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
21.3.19 IEBus Receive Interrupt Enable Register (IEIER) .......................................... 1131
21.3.20 IEBus Clock Selection Register (IECKSR) .................................................... 1133
21.3.21 IEBus Transmit Data Buffer 001 to 128 (IETB001 to IETB128) ................... 1134
21.3.22 IEBus Receive Data Buffer 001 to 128 (IERB001 to IERB128) .................... 1135
21.4 Data Format .................................................................................................................... 1136
21.4.1 Transmission Format ...................................................................................... 1136
21.4.2 Reception Format ............................................................................................ 1137
21.5 Software Control Flows .................................................................................................. 1138
21.5.1 Initial Setting .................................................................................................. 1138
21.5.2 Master Transmission ....................................................................................... 1139
21.5.3 Slave Reception .............................................................................................. 1140
21.5.4 Master Reception ............................................................................................ 1141
21.5.5 Slave Transmission ......................................................................................... 1142
21.6 Operation Timing ............................................................................................................ 1143
21.6.1 Master Transmit Operation ............................................................................. 1143
21.6.2 Slave Receive Operation ................................................................................. 1144
21.6.3 Master Receive Operation .............................................................................. 1145
21.6.4 Slave Transmit Operation ............................................................................... 1146
21.7 Interrupt Sources ............................................................................................................. 1147
21.8 Usage Notes .................................................................................................................... 1149
21.8.1 Note on Operation when Transfer is Incomplete after Transfer of
the Maximum Number of Bytes ..................................................................... 1149
Section 22 Renesas SPDIF Interface ............................................................... 1151
22.1 Overview ........................................................................................................................ 1151
22.2 Features ........................................................................................................................... 1151
22.3 Functional Block Diagram .............................................................................................. 1152
22.4 Input/Output Pins ............................................................................................................ 1153
22.5 Renesas SPDIF (IEC60958) Frame Format .................................................................... 1153
22.6 Register ........................................................................................................................... 1155
22.7 Register Descriptions ...................................................................................................... 1156
22.7.1 Control Register (CTRL) ................................................................................ 1156
22.7.2 Status Register (STAT) ................................................................................... 1161
22.7.3 Transmitter Channel 1 Audio Register (TLCA) ............................................. 1165
22.7.4 Transmitter Channel 2 Audio Register (TRCA) ............................................. 1166
22.7.5 Transmitter DMA Audio Data Register (TDAD) ........................................... 1167
22.7.6 Transmitter User Data Register (TUI) ............................................................ 1168
22.7.7 Transmitter Channel 1 Status Register (TLCS) .............................................. 1169
22.7.8 Transmitter Channel 2 Status Register (TRCS) .............................................. 1171
22.7.9 Receiver Channel 1 Audio Register (RLCA) ................................................. 1173