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Section 7 Interrupt Controller
R01UH0134EJ0400 Rev. 4.00 Page 175 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Whether IRQ interrupt requests have been detected or not can be checked by reading the IRQ7F to
IRQ0F bits in IRQRR. Writing 0 to these bits after reading them as 1 clears the result of IRQ
interrupt request detection.
The IRQ interrupt exception handling sets the I3 to I0 bits in SR to the priority level of the
accepted IRQ interrupt.
When returning from IRQ interrupt exception service routine, execute the RTE instruction after
confirming that the interrupt request has been cleared by the IRQ interrupt request register
(IRQRR) so as not to accidentally receive the interrupt request again.
7.4.4 PINT Interrupts
PINT interrupts are input from pins PINT7 to PINT0. Input of the interrupt requests is enabled by
the PINT enable bits (PINT7E to PINT0E) in the PINT interrupt enable register (PINTER). For
the PINT7 to PINT0 interrupts, low-level or high-level detection can be selected individually for
each pin by the PINT sense select bits (PINT7S to PINT0S) in interrupt control register 2 (ICR2).
A single priority level in a range from 0 to 15 can be set for all PINT7 to PINT0 interrupts by bits
15 to 12 in interrupt priority register 05 (IPR05).
When using low-level sensing for the PINT7 to PINT0 interrupts, an interrupt request signal is
sent to the interrupt controller while the PINT7 to PINT0 pins are low. An interrupt request signal
is stopped being sent to the interrupt controller when the PINT7 to PINT0 pins are driven high.
The status of the interrupt requests can be checked by reading the PINT interrupt request bits
(PINT7R to PINT0R) in the PINT interrupt request register (PIRR). The above description also
applies to when using high-level sensing, except for the polarity being reversed. The PINT
interrupt exception handling sets the I3 to I0 bits in SR to the priority level of the PINT interrupt.
When returning from IRQ interrupt exception service routine, execute the RTE instruction after
confirming that the interrupt request has been cleared by the PINT interrupt request register
(PIRR) so as not to accidentally receive the interrupt request again.