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Section 26 USB 2.0 Host/Function Module
Page 1496 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
bits when the setup stage ends, and it generates a CTRT interrupt after the interrupt status is
cleared.)
1
CTSQ = 001
control read
data stage
2
CTSQ = 010
control read
status stage
4
CTSQ = 000
idle stage
3
CTSQ = 100
control write
status stage
1
CTSQ = 101
control write
no data
status stage
5
CTSQ = 110
control transfer
sequence error
CTSQ = 000
setup stage
1
CTSQ = 011
control write
data stage
Setup token reception
Setup
token reception
Setup token reception
Error
detection
OUT token
IN token
ACK
trans-
mission
ACK
reception
ACK
reception
Note:
CTRT interrupts
(1) Setup stage completed
(2) Control read transfer status stage transition
(3) Control write transfer status stage transition
(4) Control transfer completed
(5) Control transfer sequence error
4
Error detection and IN token reception
are valid at all stages in the box.
ACK
trans-
mission
ACK
transmission
ACK
transmission
Figure 26.7 Control Transfer Stage Transitions
(6) Frame Update Interrupt
Figure 26.8 shows an example of the SOFR interrupt output timing of this module. With the host
controller function selected, an interrupt is generated at the timing at which the frame number is
updated. With the function controller function selected, the SOFR interrupt is generated when the
frame number is updated.
When the function controller function is selected, this module updates the frame number and
generates an SOFR interrupt if it detects a new SOF packet during full-speed operation. During
high-speed operation, however, this module does not update the frame number, or generates no
SOFR interrupt until the module enters the SOF locked state. Also, the SOF interpolation
function is not activated. The SOF lock state is the state in which SOF packets with different
frame numbers are received twice continuously without error occurrence.
The conditions under which the SOF lock monitoring begins and stops are as follows.